1. Technical Field
Systems and methods consistent with the present invention generally relate to Electronic Design Automation (EDA), and in particular to systems and methods for processing of netlists of System-on-Chip (SOC) designs relative to signal naming, signal connectivity and strengths of connectivity, properties of signals and groups of signals, and different levels of abstraction within an SOC description.
2. Description of the Related Art
System-On-Chip (SOC) designs are large and complex, frequently reaching sizes in excess of 50 million gates. As a result, when a new or enhanced application is to be addressed by a new design, the new design is most often a modification of a previous SOC design. Typically, an engineering organization attempts to use as much of the previous design as possible in order to save time, resources, and expense.
When attempting to reuse an existing SOC design, a common difficulty encountered by a design team is that the existing design may be poorly documented, or alternately simply exists only at a low register transfer level (RTL) description level with individual signal names which when viewed presents an overwhelming degree of complexity making it difficult to understand the design. Understanding the design is critical to modifying and reusing an existing design. Since creation of SOC designs typically require a team of many individuals, it is also common that at least some of the original designers are no longer available to explain an existing design—having either left the company or moved on to other projects.